An example of an FDSOI transistor is illustrated in FIG. 1. This type of transistor is produced on an SOI (acronym for silicon-on-insulator) substrate having a structure consisting of a stack of a silicon layer (a few nm to a few tens of nm in thickness) on a dielectric, possibly silicon dioxide, layer forming a buried dielectric layer commonly referred to as a “BOX”. The SOI substrate thus comprises a silicon substrate 1, the buried BOX layer 2 and a layer of a semiconductor such as silicon, for example, in which a channel 3, a source region 4 and a drain region 5 are produced. The channel 3 is covered with a gate dielectric 6 on which the gate 7 is deposited.
Regarding this type of component, it is more and more difficult and expensive to obtain small features using conventional optical lithography.
A number of solutions have been envisaged for future technology nodes:                preserving the same lithography technique but reducing the wavelengths used (extreme UV technology, etc.);        employing one or more electron beams; and        employing what is called a “double patterning” technique using, for example, spacers as a mask so as to double the feature density as illustrated by the series of different process steps illustrated in FIGS. 2a to 2e, showing successive lithography operations for producing, in various layers C1 and C2 features of smaller and smaller size, M1i and M2j, respectively.        
It has already been proposed to use what are called block copolymers. Under certain conditions (molar mass ratio, size and passivation of the cavities) block copolymers (BCPs) may organise into strips formed alternately by monomers of type A and B, as shown in FIG. 3a. By removing only one (type B) of the two types of block, is possible to use the remaining block (type A) as an etching mask, as illustrated in FIG. 3b. Dense features M3k of the size of the blocs are then transferred into the material of the subjacent layer C3.
This type of structure is notably described in patent WO 2011/74852 A1 enabling conductive nanostructures to be defined by removing, in succession, a first series of blocks, then a second series of blocks, or indeed even in patent applications US 2011/0117744 A1 or US 2011/0081777 A1.
Certain scientific publications also disclose processes allowing the features of transistor structures to be produced, notably the articles of L.-W. Cheng et al. “Top-gated FETs/inverters with diblock copolymer self-assembled 20 nm contact holes” IEDM, pages 1-4, 2009; or indeed even that of L.-W. Cheng et al. “Experimental demonstration of aperiodic patterns of directed self-assembly by block copolymer lithography for random logic circuit layout” IEDM, pages 33.2.1-33.2.4, 2010. In this publication the copolymers self assemble to form holes that are 18 nm in diameter. These holes are filled with platinum in order to create contacts. The electrical performance of a CMOS inverter produced using this technique is also reported.